Interconnect lines electrically connect devices within an integrated circuit (IC). IC devices may include one or more complimentary metal oxide semiconductor (CMOS) transistors having diffused source and drain regions separated by channel regions, and gates that are located over the channel regions. In practice, an IC may include thousands or millions of devices, such as CMOS transistors.
Interconnect lines of ICs generally take the form of patterned metallization layers. Interconnect lines may be formed one on top of another with an electrically insulating material therebetween. As will be more fully described below, one interconnect line may be formed under another interconnect line and electrically connected thereto by one or more tungsten plugs.
ICs are manufactured on silicon substrates, often called wafers, using conventional photolithographic techniques. FIGS. 1-8 show a cross-sectional view of an IC during a portion of its manufacture. More particularly, FIG. 1 shows a first dielectric layer 12, a first metallization layer 14, and a photoresist layer 16 formed over substrate 10. Layers 12-16 are formed using conventional techniques such as chemical vapor deposition, sputtering, or spin-on coating.
First metallization layer 14 can be formed into a first interconnect line. This first interconnect line can be formed by selectively exposing photoresist layer 16 to light passing through a patterned reticle (not shown). Photoresist areas of layer 16 exposed to light are subsequently removed using conventional development techniques. FIG. 2 shows the substrate 10 of FIG. 1 after development of photoresist layer 16 to form photoresist mask pattern 20.
Once the photoresist mask pattern 20 is formed, a plasma etching operation is applied to the IC shown in FIG. 2 to remove portions of metallization layer 14 that are not covered by photoresist mask pattern 20. FIG. 3 shows the IC of FIG. 2 after plasma etching thereof. The plasma etching operation results in first interconnect line 22.
FIG. 4 shows the IC of FIG. 3 after a second dielectric layer 24 is deposited thereon. Although not shown, photoresist mask pattern 20 is removed prior to formation of second dielectric layer 24. The second dielectric layer 24 and the first dielectric layer 12 may be formed from an insulating material such as silicon dioxide.
FIG. 5 shows the IC of FIG. 4 after a via 26 is formed within the second dielectric layer 24. As is well known in the art, vias, such as via 26, are formed by depositing a photoresist layer (not shown) over dielectric layer 24, selectively exposing this photoresist layer to light passing through a patterned reticle having via hole patterns formed therein, developing and removing the exposed photoresist to form a photoresist via mask pattern, etching any dielectric layer 24 exposed through the photoresist via mask pattern, and removing the remaining photoresist via mask after etching dielectric layer 24.
Once the vias are formed within the second dielectric layer 24, the vias are filled with an electrically conductive material such as tungsten. As well is known in the art, vias, such as via 26, are filled by depositing a barrier film by sputter or chemical vapor deposition, depositing a conductive film by sputter or chemical vapor deposition, and then removing the conductive film, and possibly removing the barrier film, over dielectric layer 24, but not inside the via 26. The barrier film is typically comprised of titanium, titanium nitride, or a titanium/titanium nitride stack. The conductive film is typically tungsten. The conductive film, and possibly the barrier film, is removed by plasma etching, chemical mechanical polishing, or wet etching. FIG. 6 shows via 26 of FIG. 5 filled with tungsten, thereby forming tungsten plug 30.
After the tungsten plugs are formed, a second metallization layer is formed over dielectric layer 24 and the tungsten plugs, including tungsten plug 30. This metallization layer is typically comprised of a metal stack that includes any combination of one or more the following: titanium, titanium nitride, aluminum, an aluminum copper alloy, or an aluminum silicon copper alloy. This metallization layer is then patterned using conventional photolithography and plasma etching to form an additional layer of interconnect lines. FIG. 7 shows the IC of FIG. 6 with a second interconnect line 32 formed thereon. The second interconnect line 32 is electrically coupled to the first interconnect line 22 via the tungsten plug 30. First interconnect line 22 may be coupled at one end to a first device (i.e., a first CMOS transistor). The second interconnect line 32 may be coupled to a second device (i.e., a second CMOS transistor) or coupled to connections which lead to the outside of the chip package. Accordingly, the structure of the first interconnect line 22, tungsten plug 30, and second interconnect line 32, function to interconnect the first and second IC devices or function to interconnect an IC device and external package connections.
As is well known in the art, conventional plasma etching to form interconnect lines (e.g., interconnect line 32) often leaves residual polymer (not shown) on the sides of the interconnect lines. To remove this residual polymer on the sides of the interconnect lines, a liquid cleaning solution is often used after plasma etch. Further, conventional plasma etching to form interconnect line 32 may leave a positive electrical charge on interconnect line 32, and thus, tungsten plug 30 and first interconnect line 22. For purposes of explanation, it will be presumed that the structure consisting of first interconnect line 22, tungsten plug 30, and second interconnect line 32 is a floating structure such that both interconnect lines 22 and 32 and tungsten plug 30 will be positively charged before the polymer residue removal process.
After plasma etching, the IC shown in FIG. 7 is exposed to a cleaning solution to remove any polymer remaining after the plasma etching step. Typically this cleaning solution may be alkaline or basic in nature (i.e. pH is greater than 7), however, acidic solutions (i.e. pH is less than 7) can also be used. Although the cleaning solution works well in removing polymer residues, one, some, or all of the tungsten plugs that are exposed to the cleaning solution may dissolve or erode away during the polymer residue removal process. The cause is electrochemical corrosion caused by two dissimilar conductive materials being in contact, the interconnect line and the tungsten plug, while both conductive materials are simultaneously in contact with an electrolyte, the cleaning solution or rinsing solution, during the polymer removal process.
More and more devices are packed into smaller ICs. As such, the density of devices and interconnect lines in ICs has dramatically increased over the years. Unfortunately, this dense integration of devices and interconnect lines has the effect of pushing the limits of conventional photolithography patterning, which necessarily makes photolithography masks misalignments more likely to occur. An increase in misalignments will result in an increase of exposed tungsten plugs.
FIG. 7 illustrates the effects of misalignment of photolithography masks. More particularly, the misalignment of photolithography masks used to create second interconnect line 32 produces a misalignment of second interconnect line 32 with respect to tungsten plug 30. As a result of this misalignment, tungsten plug 30 will be exposed to cleaning solution during the polymer residue removal step described above.
FIG. 8 illustrates how tungsten plug 30 could be corroded by the cleaning or rinsing solution of the polymer residue removal process. As seen in FIG. 8, a substantial portion of tungsten plug 30, is removed by the aforementioned corrosion. Tungsten plug corrosion may have adverse effects on performance of the IC. For example, corrosion of tungsten plug 30 shown in FIG. 8 may be so extensive that first interconnect line 22 is no longer electrically coupled to second interconnect line 32 thereby creating an open circuit therebetween. IC devices coupled to second interconnect line 32 could be electrically isolated from IC devices coupled to first interconnect line 22 thereby resulting in an IC that fails to function for its intended purpose.
Clearly, there is a need to avoid tungsten plug corrosion in the manufacture of ICs. In 1998, a paper was published by S. Bothra, H. Sur, and V. Liang, entitled, “A New Failure Mechanism by Corrosion of Tungsten in a Tungsten Plug Process,” IEEE Annual International Reliability Physics Symposium, pages 150-156. This paper, which is incorporated herein by reference in its entirety, describes some techniques for preventing tungsten plug corrosion. These techniques involve discharging the tungsten plugs prior to immersion in alkaline cleaning solution to remove polymer residue. In one technique described in the paper, tungsten plug discharge is accomplished by flooding ICs with an electron-beam prior to polymer residue removal. The paper found that blanket electron-beam flooding of ICs was enough to discharge exposed tungsten plugs, such as the exposed tungsten plug shown in FIG. 7, such that the exposed tungsten plugs were found to remain in tact after subsequent emersion in the alkaline cleaning solution. The paper said this method was found to be effective without any associated drawbacks. The paper stated that a variety of devices for discharging surfaces to prevent ESD (electrostatic discharge) failures in the clean rooms are available in the market place. However, the paper found that experiments with a few hand-held devices failed, presumably because the electron density is not high enough. It is noted that this paper should not be considered prior art to the invention claimed herein.